1. Field of the Invention
This invention relates to methods and apparatus for programming programmable logic integrated circuits such as field programmable gate arrays ("FPGAs") and many kinds of programmable logic devices ("PLDs").
2. Description of Related Art
Extremely powerful and flexible programmable logic circuit architectures are known as shown, for example, by Pedersen U.S. Pat. No. 5,260,610 and Cliff U.S. Pat. No. 5,260,611, both of which are hereby incorporated by reference herein. These architectures include large numbers of logic modules, each of which is programmable to perform any of several relatively elementary logic functions. An extensive network of conductors is provided for programmably interconnecting these logic modules in order to provide much more complex logic functions. These logic circuits include very large numbers of programmable elements. Each logic module has a substantial number of these elements, and the interconnection network also requires many such elements to produce the desired interconnections between logic modules.
A typical technique for programming the programmable elements in devices of the type described above is to employ shift registers as shown, for example, in Wahlstrom U.S. Pat. No. 3,473,160 and Freeman U.S. Pat. No. 4,870,302. Each shift register stage controls an associated logic or switching element. Programming data is shifted through the shift register or registers until the data desired for controlling each logic or switching element is stored in the shift register stage associated with that element. A disadvantage of this approach is that shift registers are relatively complex and require substantial numbers of conductors for interstage data transfer, clocking, etc. Thus in complex logic circuit structures, the shift register approach to programming may take up excessive space and other resources, and may even become a limiting factor in the design of the device. The testing of shift register programmed devices is also relatively cumbersome because the shift register can only be tested by shifting data all the way through it. If, as is common in very complex logic circuits, the shift registers are long, it may take a relatively long time to shift test data through them.
A more modern technique for programming the programmable elements in devices of the type described above is to employ multiple programming elements connected in a series or chain in which the serial interconnections are controlled by addressable switches as shown in Cliff U.S. Pat. No. 5,237,219.
The programmable elements in the series are programmed one after another starting with the one which is most remote from the data source. This most remote element is programmed by turning on all the programmable element switches and having the data source supply the data desired for storage in the most remote programmable element. Because all of the programmable element switches are on, this data flows through all of the programmable elements to the most remote one. The programmable element switch just upstream from the most remote programmable element is then turned off and the data source supplies the data desired for storage in the second-most-remote programmable element. This data flows through the series of programmable elements to the second-most-remote programmable element. The most remote programmable element is unaffected and continues to store the previously applied data because the programmable switch upstream from it has been turned off. The programmable element switch upstream from the second-most-remote programmable element is now turned off and the data source supplies the data to be stored in the third-most-remote programmable element. This process continues until the desired data has been stored in all of the programmable elements and all of the programmable element switches have been turned off. Any number of series of programmable elements can be programmed at the same time in parallel.
A characteristic of this approach is that the data desired for storage in the programmable element being programmed at a particular instant is allowed time to pass through all programmable elements and switches upstream from the programmable element being programmed before programming of the next programmable element begins. The time it takes data to pass through all the upstream programmable elements adds to the total time required to program the device and amounts to an unproductive delay.
Thus, there has been a need in the art for a method and apparatus for programming a programmable logic circuit, that allows multiple data items to move down a series of programmable elements simultaneously while maintaining their individual integrity.